View EM78P5830AA_1187440.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EM785830AA
8-BIT MICRO-CONTROLLER
Version 1.6
ELAN MICROELECTRONICS CORP. No. 12, Innovation 1st RD., Science-Based Industrial Park Hsin Chu City, Taiwan TEL: (03) 5639977 FAX: (03)5630118
Version History
Specification Revision History
Version EM785830AA 1.0 1.1 1.2 1.3 1.4 1.5 Content Initial version Add 17.9MHz main CLK Add code option "ADIS" to determine AD channel 1. Change "ADIS" define 2. ADD eFHP5830A, eFHP5830AA, and eFHP5830BA package 1. ADD the description about ADC's offset voltage 1. Modify stack level from 16 to 12 2. Modify program ROM size from 4K to 16K 3. Rename "eFH5830A" to eFH5830AA 4. Remove IDLE mode 5. Change AD channel from 8 to 4 6. Remove 17.9MHz main CLK 1.Rename from eFH5830AA to EM785830AA
1.6
Relative to EM785830AA's ROM-less, OTP and mask:
ROM-less ICE5830 OTP EM78P5830A EM78P5830AA Mask EM785830AA
Difference between EM785830AA/EM78P5830A/EM78P5830AA
Some differences are between EM78P5830A, EM78P5830AA and EM78P5830BA, these difference are list at next table:
EM785830AA ADIS (code option) VERSEL (code option) PHO (code option) MS (IOCC page1 bit0) AD resolution Stack number
Un-effect (4 channel only) Must = 0 Must = 0 Must = 1 10 bit 12
EM78P5830A EM78P5830AA
Un-effect (4 channel only) Un-effect Un-effect Must = 1 8 bit 16 Un-effect (4 channel only) Must = 0 Must = 0 Un-effect 10 bit 16
User Application Note
(Before using this chip, take a look at the following description note, it includes important messages.) 1. There are some undefined bits in the registers. The values in these bits are unpredicted. These bits are not allowed to use. We use the symbol "-" in the spec to recognize them. A fixed value must be write in some specific unused bits by software or some unpredicted wrong will occur. These bits are as below.
Register R7 RA RA RD RD Register PAGE 1 0 2 0 0 Default value Bit 1 7 0~7 0~2 4 0 0 0 0 X Initial Setting value (by user software) 0 0 0 0 1 Effect RAM access will error Un-expect error Un-expect error Power consumption increase Un-expect error
EM785830AA 8-bit Micro-controller
RD RE IOC5 IOC6 IOC6 IOC7 IOC7 IOC8 IOC8 IOC9 IOCA IOCB IOCC IOCC IOCE IOCF 0 0 0 0 1 0 1 0 1 1 1 0 0 1 0 0 5~6 0~3 5~7 0~1 0~1 1~2;7 1~2;7 0~7 0~7 0~7 3,6 0~7 0;3~7 2~7 0~3 4~6 X 1 1 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Un-expect error Un-expect error Power consumption increase Power consumption increase Power consumption increase Power consumption increase Power consumption increase Power consumption increase Power consumption increase Un-expect error Power consumption increase Power consumption increase Power consumption increase Un-expect error Un-expect error Un-expect error
2. You will see some names for the register bits definitions. Some name will be appear very frequently in the whole spec. The following describes the meaning for the register's definitions such as bit type, bit name, bit number and so on.
RA PAGE0
7 RAB7 R/W-0 Bit type Bit name Bit number
6 RAB6 R/W-0
5 BAB5 R-1
4 RAB4 R/W-1
read/write (default value=1)
3 X
2 RAB2 R
1 RAB1 R-0
0 RAB0 R/W
read/write (w/o default value)
read/write (default value=0)
read only (w/o default value)
(undefined) not allowed to use read only (default value=1) read only (default value=0)
Register name and its page
3. Always set IOCC PAGE1 bit 0 = 1 otherwise partial ADC function cannot be used. 4. Please do not switch MCU operation mode from normal mode to sleep mode directly. Before into sleep mode, please switch MCU to green mode. 5. While switching main clock (regardless of high freq to low freq or on the other hand), adding 6 instructions delay (NOP) is required. 6. Offset voltage will effect ADC's result, please refer to figure 16 to detail.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
1
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
I. General Description
The EM785830AA is an 8-bit RISC type microprocessor with low power, high speed CMOS technology. There are 16Kx13 bits ROM within it. This integrated single chip has an on_chip watchdog timer (WDT, data RAM, programmable real time clock/counter, internal interrupt, power down mode, 4-channel 10-bit A/D converter, two channel PWM output, SPI and tri-state I/O.
II. Feature
CPU * Operating voltage : 2.2V~5.5V at main CLK less then 3.58MHz.
E E E E E E E E E Main CLK(Hz) Under 3.58M 7.16M 10.74M 14.3M Operating Voltage(min) 2.2 2.5 3 3.6 16k x 13 on chip Program Memory 0.5k x 8 on chip data RAM Up to 21 bi-directional tri-state I/O ports(4 shared with AD input; 1 shared with external interrupt input ) 12 level stack for subroutine nesting 8-bit real time clock/counter (TCC) Two 8-bit counters : COUNTER1 and COUNTER2 On-chip watchdog timer (WDT) 99.9H single instruction cycle commands Four modes (Main clock can be programmed from 447.829k to 14.3MHz generated by internal PLL) Mode CPU status Main clock 32.768kHz clock status Sleep mode Turn off Turn off Turn off Green mode Turn on Turn off Turn on Normal mode Turn on Turn on Turn on 7 level Normal mode frequency : 447.8K , 895.7K , 1.79M , 3.58M , 7.16M , 10.75M and 14.3MHz. Input port interrupt function Dual clocks operation (Internal PLL main clock , External 32.768KHz) Serial Peripheral Interface (SPI) : a kind of serial I/O interface Interrupt flag available for the read buffer full or transmitter buffer empty. Programmable baud rates of communication Three-wire synchronous communication. (shared with IO)
E E E
SPI
E E E E
PWM
E Dual PWM (Pulse Width Modulation) with 10-bit resolution E Programmable period (or baud rate) E Programmable duty cycle
ADC * Operating : 2.5Va 5.5V * 4 channel 10-bit successive approximation A/D converter * Internal (VDD) or external reference POR * Power-on voltage detector reset PACKAGE
EM78P5830AM, EM78P5830AAM, EM785830AAM 28 pin SOP EM78P5830AP, EM78P5830AAP, EM785830AAP 28 pin PDIP
III. Application
General products
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
2
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
IV. Pin Configuration
AVSS P67 ADR/P66 AD6/P65 AD5/P64 AD4/P63 AD3/P62 XIN XOUT /RESET P76/SCK P75/SDO P74/SDI P73/INT3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PLLC AVDD NC P97 P96 P95 P94 P93 P92 P91 P90 PC2/PWM 2 PC1/PWM 1 P70/INT0
EM785830AAP, EM785830AAM EM78P5830AP, EM78P5830AM EM78P5830AAP, EM78P5830AAM
Fig.1 Pin assignment
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
3
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
V. Functional Block Diagram
CPU DATA RAM CONTROL REGISTER
TIM ING CONTROL
TIM ER TCC COUNTER1 COUNTER2 WDT
I/O PORT
ROM RAM
SPI PWM 10-bit A/D
Fig.2a Block diagram
XIN XOUT PLLC
WDT timer ROM R2 STACK
Oscillator timing control R1(TCC)
Prescaler Interrupt control General RAM Instruction decoder R4 Instruction register R3 R5 ALU
DATA RAM
Control sleep and wakeup on I/O port
ACC
DATA & Control Bus
IOC6 SPI PWM 10-bit A/D R6 PORT6
IOC7 R7 PORT7
IOC9 R9 PORT9
IOCC RC PORTC
P62~P67
P70 P73~P76
P90~P97
PC1~PC2
Fig.2b Block diagram
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
4
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
VI. Pin Descriptions
PIN POWER AVDD AVSS CLOCK XIN XOUT PLLC I/O POWER POWER I O I DESCRIPTION Power Ground Input pin for 32.768 kHz oscillator Output pin for 32.768 kHz oscillator Phase loop lock capacitor, connect a capacitor 0.047u to 0.1u to the ground. ADC reference input. Shared with PORT66 ADC input channel 3. Shared with PORT62 ADC input channel 4. Shared with PORT63 ADC input channel 5. Shared with PORT64 ADC input channel 6. Shared with PORT65 Master: output pin, Slave: input pin. This pin shared with PORT76. Output pin for serial data transferring. This pin shared with PORT75. Input pin for receiving data. This pin shared with PORT74. Pulse width modulation output channel 1 This pin shared with PORTC1 Pulse width modulation output channel 2 This pin shared with PORTC2 PORT6 can be INPUT or OUTPUT port each bit. PORT7 can be INPUT or OUTPUT port each bit. PORT9 can be INPUT or OUTPUT port each bit. PORTC can be INPUT or OUTPUT port each bit. Interrupt sources. Once PORT70 has a falling edge or rising edge signal (controlled by CONT register), it will generate a interruption. Interrupt sources which has the same interrupt flag. Any pin from PORT73 has a falling edge signal, it will generate a interruption. Low reset
10-bit 4 channel A/D VREF I (P66) AD3 I (P62) AD4 I (P63) AD5 I(P64) AD6 I(P65) SPI SCK IO (PORT76) SDO O (PORT75) SDI I (PORT74) PWM PWM1 O PWM2 IO P62 ~P67 P70 ; P73~P76 P90 ~ P97 PC1 ~ PC2 INT0 INT3 /RESET O
I/O I/O I/O I/O PORT70 PORT73 I
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
5
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
VII. Functional Descriptions VII.1 Operational Registers
Register configuration
Addr 00 01 02 03 04 05 06 07 08 09 R PAGE registers R PAGE0 R PAGE1 R PAGE2 Indirect addressing TCC PC Page, Status RAM bank, RSR Port5 I/O data, SPI control Program ROM page Port6 I/O data SPI data buffer Port7 I/O data Data RAM bank Data RAM address Data RAM data buffer R PAGE3
PWM control Duty of PWM1 PWM1 control Duty of PWM1 Period of PWM1 Duty of PWM2 PWM2 control Duty of PWM2 Period of PWM2
Port9 I/O data
0A PLL, Main clock, WDTE 0B 0C 0D 0E 0F 10 : 1F 20 : 3F PortC I/O data Interrupt flag Interrupt flag 16 bytes Common registers Bank0~Bank3 Common registers (32x8 for each bank)
ADC output data buffer Counter1 data Counter2 data
IOC PAGE registers Addr IOC PAGE0 IOC PAGE1 00 01 02 03 04 05 Port5 I/O control, 06 Port6 I/O control Port6 switches 07 Port7 I/O control Port7 pull high 08 09 Port9 I/O control 0A 0B ADC control 0C PortC I/O control 0D Clock source(CN1,CN2) Prescaler(CN1,CN2 )
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
6
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
0E 0F 10 : 1F 20 : 3F Interrupt mask
VII.2 Operational Register Detail Description
R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). Example: Mov A, @0x20 ;store a address at R4 for indirect addressing Mov 0x04, A Mov A, @0xAA ;write data 0xAA to R20 at bank0 through R0 Mov 0x00, A
R1 (TCC)
TCC data buffer. Increased by 16.384KHz or by the instruction cycle clock (controlled by CONT register). Written and read by the program as any other register.
R2 (Program Counter)
The structure is depicted in Fig.3. Generates 16k x 13 on-chip ROM addresses to the relative programming instruction codes. "JMP" instruction allows the direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2, A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. "TBL" allows a relative address added to the current PC, and contents of the ninth and tenth bits don't change. The most significant bit (A10~A11) will be loaded with the contents of bit PS0~PS1 in the status register (R5 PAGE0) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction. If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at page0. The CPU will store ACC, R3 status and R5 PAGE automatically, and they will be restored after instruction RETI.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
7
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
R5(PAGE) CALL and INTERRUPT A13 A12 A11 A10 0000 0001 0010 A9 A8 PAGE0 PAGE1 PAGE2 A7~A0 00000~003FF 00400~007FF 00800~00BFF RET RETL RETI STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 STACK9 STACK10 STACK11 STACK12
store ACC,R3,R5(PAGE) restore
: : :
1111
PAGE15
05400~057FF
Fig.3 Program counter organization R3 (Status, Page selection)
(Status flag, Page selection bits) 7 6 5 4 3 2 1 0 RPAGE1 RPAGE0 IOCPAGE T P Z DC C R/W-0 R/W-0 R/W-0 R R R/W R/W R/W Bit 0(C) : Carry flag Bit 1(DC) : Auxiliary carry flag Bit 2(Z) : Zero flag Bit 3(P) : Power down bit Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4(T) : Time-out bit Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
EVENT WDT wake up from sleep mode WDT time out (not sleep mode) /RESET wake up from sleep Power up Low pulse on /RESET T 0 0 1 1 x P 0 1 0 1 X x : don't care REMARK
Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page Please refer to Fig.4 control register configuration for details. 0/1 IOC page0 / IOC page1 Bit 6(RPAGE0 ~ RPAGE1) : change R5 ~ RE to another page Please refer to VII.1 Operational registers for detail register configuration. (RPAGE1,RPAGE0) (0,0) (0,1) (1,0) (1,1) R page # selected R page 0 R page 1 R page 2 R page 3
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
8
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller R4 (RAM selection for common registers R20 ~ R3F))
(RAM selection register) 7 6 5 4 3 2 1 0 RB1 RB0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 R/W-0 R/W-0 R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode. Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F These selection bits are used to determine which bank is activated among the 4 banks for 32 register (R20 to R3F). Please refer to VII.1 Operational registers for details.
R5 (PORT5 I/O data, Program page selection, SPI control , PWM control)
PAGE0 (PORT5 I/O data register, Program page register) 7 6 5 4 3 2 1 PS3 PS2 PS1 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 3 (PS0 ~ PS3): Program page selection bits PS3 PS2 PS1 PS0 Program memory page (Address) 0 0 0 0 Page 0 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 : : : : : : : : : : 1 1 1 0 Page 14 1 1 1 1 Page 15 0 PS0 R/W-0
User can use PAGE instruction to change page to maintain program page by user. Bit 4: (undefined) not allowed to use. This bit must clear to 0 or some unpredicted wrong will occur. Bit 5 ~ Bit 7: (undefined) not allowed to use. These bits are not sure be 0 or 1. PAGE2 (SPI control) 7 6 RBF SPIE R/W-0 R/W-0 SBR2 0 0 0 0 1 1 1 1
5 SRO R/W-0 SBR1 0 0 1 1 0 0 1 1
4 SE R/W-0
3 SCES R/W-0 SBR0 0 1 0 1 0 1 0 1
2 SBR2 R/W-0
1 SBR1 R/W-0
0 SBR0 R/W-0 Baud rate Fsco Fsco/2 Fsco/4 Fsco/8 Fsco/16 Fsco/32 16.384k
Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits Mode Master Master Master Master Master Master Slave Master
Fsco = CPU instruction clock For example : If PLL is enabled and main clock is selected to 3.5826MHz, the instruction clock is 3.5826MHz/2 Fsco=3.5862MHz/2 If PLL is enabled and main clock is selected to 3.5826MHz, the instruction clock is 0.895MHz/2
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
9
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
Fsco=0.895MHz/2 If PLL is disabled, the instruction clock is 32.768kHz/2 Fsco=32.768kHz/2. Bit 3 (SCES) : SPI clock edge selection bit 1 Data shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level. 0 Data shifts out on rising edge, and shifts in on falling edge. Data is hold during the low level. Bit 4 (SE) : SPI shift enable bit 1 Start to shift, and keep on 1 while the current byte is still being transmitted. 0 Reset as soon as the shifting is complete, and the next byte is ready to shift. This bit has to be reset in software. Bit 5 (SRO) : SPI read overflow bit 1 A new data is received while the previous data is still being hold in the SPIB register. In this situation, the data in SPIS register will be destroyed. To avoid setting this bit, users had better to read SPIB register even if the transmission is implemented only. 0 No overflow, This can only occur in slave mode. Bit 6 (SPIE) : SPI enable bit 1 Enable SPI mode 0 Disable SPI mode Bit 7 (RBF) : SPI read buffer full flag 1 Receive is finished, SPIB is full. 0 Receive is not finish yet, SPIB is empty.
SDO
SDI
Master Device
R5 page1
SPIR register SPIW register
Salve Device
SPIS Reg
Bit7 Bit 0
SDI
SDO
SPI module
SCK
SCK
Fig.4 Single SPI Master / Salve Communication Fig. 4 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI, however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted on a basis of both the clock rate and the selected edge.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
10
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
Read R5 RBF RBFI
Write R5 SPIWC
SPIR reg.
SPIW reg.
set to 1 SPIE Buffer Full Detector SDI
SDI/P74
MUX
SPIS reg.
PORT62 bit 0 SDO
shift right bit 7
SDO/P75
SPIC reg. (R4 page1)
MUX
PORT61 Edge Select
SPIE 0
3
SBR0 ~SBR2
SBR2~SBR0
3 2
Noise Filter
Clock Select
Tsco
16.38kHz
Prescaler 4, 8, 16, 32, 64, 128
Edge Select SCK
SCK PORT60
MUX
SCK/P76
SPIE
Fig.5 SPI structure
SPIC reg. : SPI control register SDO: Serial data out SDI: Serial data in SCK: Serial clock RBF : Set by buffer full detector, and reset in software. RBFI : Interrupt flag. Set by buffer full detector, and reset in software. Buffer Full Detector : Sets to 1, while an 8-bit shifting is complete. SE : Loads the data in SPIW register, and begin to shift SPIE : SPI control register SPIS reg. : Shifting byte out and in. The MSB will be shifted first. Both the SPIS register and the SPIW register are loaded at the same time. Once data being written to, SPIS starts transmission / reception. The received data will be moved to the SPIR register, as the shifting of the 8-bit data is complete. The RBF (Read Buffer Full ) flag and the RBFI(Read Buffer Full Interrupt) flag are set. SPIR reg. : Read buffer. The buffer will be updated as the 8-bit shifting is complete. The data must be read before the next reception is finished. The RBF flag is cleared as the SPIR register read. SPIW reg. : Write buffer. The buffer will deny any write until the 8-bit shifting is complete. The SE bit will be kept in 1 if the communication is still under going. This flag must be cleared as the shifting is finished. Users can determine if the next write attempt is available. SBR2 ~ SBR0: Programming the clock frequency/rates and sources. Clock select : Selecting either the internal instruction clock or the external 16.338KHz clock as the shifting clock. Edge Select : Selecting the appropriate clock edges by programming the SCES bit
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
11
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
SCK
(SCES=0)
SCK
(SCES=1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SDO
SDI
RBF
Shift data in
Shift data out
Clear by software
Fig.6 SPI timing PAGE3 (PWMCON) 7 6 5 4 3 2 1 PWM2E PWM1E T2EN T1EN T2P1 T2P0 T1P1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 1 ( T1P0 ~ T1P1 ): TMR1 clock prescale option bits. T1P1 T1P0 Prescale 0 0 1:2(Default) 0 1 1:8 1 0 1:32 1 1 1:64 Bit 2 ~ Bit 3 ( T2P0 ~ T2P1 ): TMR2 clock prescale option bits. T2P1 T2P0 Prescale 0 0 1:2(Default) 0 1 1:8 1 0 1:32 1 1 1:64 Bit 4 (T1EN): TMR1 enable bit 0 TMR1 is off (default value). 1 TMR1 is on. Bit 5 (T2EN): TMR2 enable bit 0 TMR2 is off (default value). 1 TMR2 is on.
__________________________________________________________________________________________________________________________________________________________________
0 T1P0 R/W-0
* This specification is subject to be changed without notice.
12
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
Bit 6 (PWM1E): PWM1 enable bit 0 PWM1 is off (default value), and its related pin carries out the PC1 function; 1 PWM1 is on, and its related pin will be set to output automatically. Bit 7 (PWM2E): PWM2 enable bit 0 PWM2 is off (default value), and its related pin carries out the PC2 function. 1 PWM2 is on, and its related pin will be set to output automatically.
R6 (PORT6 I/O data, SPI data buffer)
PAGE0 (PORT6 I/O data register) 7 6 5 4 3 2 P67 P66 P65 P64 P63 P62 R/W R/W R/W R/W R/W R/W Bit0 ~Bit1: Unused register. These two bits are not allowed to use. Bit2 ~ Bit7 (P62 ~ P67) : 6-bit PORT6(2~7) I/O data register User can use IOC register to define input or output each bit. 1 X 0 X -
PAGE1 : (undefined) not allowed to use PAGE2 (SPI data buffer) 7 6 5 4 3 2 1 0 SPIB7 SPIB6 SPIB5 SPIB4 SPIB3 SPIB2 SPIB1 SPIB0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer If you write data to this register, the data will write to SPIW register. If you read this data, it will read the data from SPIR register. Please refer to figure7 PAGE3 (DT1L: the Least Significant Byte ( Bit 7 ~ Bit 0) of Duty Cycle of PWM1) 7 6 5 4 3 2 1 0 PWM1[7] PWM1[6] PWM1[5] PWM1[4] PWM1[3] PWM1[2] PWM1[1] PWM1[0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 A specified value keeps the output of PWM1 to stay at high until the value matches with TMR1.
R7 (PORT7 I/O data, Data RAM bank)
PAGE0 (PORT7 I/O data register) 7 6 5 4 3 2 1 0 X P76 P75 P74 P73 X X P70 R/W R/W R/W R/W R/W Bit 0 ; Bit3 ~ Bit 7 (P73 ~ P76) : 5-bit PORT7 I/O data register User can use IOC register to define input or output each bit. Bit1~2, Bit 7: Unused register. These three bits are not allowed to use. PAGE1 (Data RAM bank selection bits) 7 6 5 4 3 2 1 0 AD9 AD8 ADRES 0 RAM_B0 R R R/W-0 R/W-0 R/W-0 Bit 0(RAM_B0) : Data RAM bank selection bits Each bank has address 0 ~ address 255 which is total 256 (0.25k) bytes RAM size. Data RAM bank selection : (Total RAM = 0.5K) RAM_B0 RAM bank 0 Bank0 1 Bank1 Bit 1 : (undefined) not allowed to use. This bit must clear to 0.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
13
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
Bit 2(ADRES) : Resolution selection for ADC 0 ADC is 8-bit resolution When 8-bit resolution is selected, the most significant(MSB) 8-bit data output of the internal 10-bit ADC will be mapping to RB PAGE1 so R7 PAGE1 bit 4 ~5 will be of no use. 1 ADC is 10-bit resolution When 10-bit resolution is selected, 10-bit data output of the internal 10-bit ADC will be exactly mapping to RB PAGE1 and R7 PAGE1 bit 4 ~5. Bit 3 : (undefined) not allowed to use Bit 4 ~ Bit 5(AD8 ~ AD9) : The most significant 2 bit of 10-bit ADC conversion output data Combine these two bits and RB PAGE1 as complete 10-bit ADC conversion output data. Bit 6 ~ Bit 7: (undefined) not allowed to use. PAGE2 : (undefined) not allowed to use PAGE3 (DT1H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM1) 7 6 5 4 3 2 1 0 PWM1[9] PWM1[8] R/W-0 R/W-0 Bit 0 ~ Bit 1 (PWM1[8] ~ PWM1[9]): The Most Significant Byte of PWM1 Duty Cycle A specified value keeps the PWM1 output to stay at high until the value matches with TMR1. Bit 2 Bit 7 : unused
R8 (Data RAM address, PWM1 period)
PAGE0: (undefined) not allowed to use PAGE1 (Data RAM address register) 7 6 5 4 3 2 1 0 RAM_A7 RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 7 (RAM_A0 ~ RAM_A7) : data RAM address The data RAM bank's selection is from R7 PAGE1 bit0 (RAM_B0). PAGE2: (undefined) not allowed to use) PAGE3(PRD1): Period of PWM1 7 6 5 4 3 2 1 0 PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 The content of this register is a period (time base) of PWM1. The frequency of PWM1 is the reverse of the period.
R9 (PORT9 I/O data, Data RAM data buffer)
PAGE0 (PORT9 I/O data register) 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register User can use IOC register to define input or output each bit. PAGE1 (Data RAM data register) 7 6 5 4 3 2 1 0 RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 7 (RAM_D0 ~ RAM_D7) : Data RAM's data register.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
14
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
The address for data RAM is accessed from R8 PAGE1. The data RAM bank is selected by R7 PAGE1 Bit0 (RAM_B0). PAGE2 : (undefined) not allowed to use PAGE3 (DT2L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle of PWM2) 7 6 5 4 3 2 1 0 PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
A specified value keeps the output of PWM2 to stay at high until the value matches with TMR2.
RA (PLL, Main clock selection, Watchdog timer)
PAGE0 (PLL enable bit, Main clock selection bits, Watchdog timer enable bit) 7 6 5 4 3 2 1 0 0 PLLEN CLK2 CLK1 CLK0 X X WDTEN R/W-0 R/W-0 R/W R/W R/W R/W-0 Bit 0(WDTEN) : Watch dog control bit User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler. 0/1 disable/enable Bit 1~Bit 2 : Unused, these 2 bits are not allowed to use. Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below. PLLEN 1 1 1 1 1 1 1 1 0 CLK2 CLK1 CLK0 Sub clock MAIN clock CPU clock 447.829kHz (Normal mode) 895.658kHz (Normal mode) 1.791MHz (Normal mode) 3.582MHz (Normal mode) 7.165MHz (Normal mode) 10.747MHz (Normal mode) 14.331MHz (Normal mode) 32.768kHz (Green mode) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 don't care don't care don't care 32.768kHz 447.829kHz 32.768kHz 895.658kHz 32.768kHz 1.791MHz 32.768kHz 3.582MHz 32.768kHz 7.165MHz 32.768kHz 10.747MHz 32.768kHz 14.331MHz Can't allowed to use 32.768kHz don't care
Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register 0/1 disable PLL/enable PLL If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode (low frequency, 32768 Hz).
447.8293kHz ~14.3MHz
CLK2 ~ CLK0
PLL circuit
ENPLL
1
switch
0
System clock
Sub-clock 32.768kHz
Fig.7 The relation between 32.768kHz and PLL
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
15
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
Bit 7: Unused register. Always keep this bit to 0 or some un-expect error will happen! The status after wake-up and the wake-up sources list as the table below. Wakeup signal SLEEP mode RA(7,6)=(0,0) + SLEP No function
TCC time out IOCF bit0=1 COUNTER1 time out IOCF bit1=1 COUNTER2 time out IOCF bit2=2 WDT time out PORT7 (0,3)
No function No function Reset and jump to address 0 Reset and Jump to address 0
PORT70 's wakeup function is controlled by IOCF bit 3. It's falling edge or rising edge trigger (controlled by CONT register bit7). PORT73 's wakeup function is controlled by IOCF bit 5. It is falling edge trigger. PAGE1,2 : (undefined) not allowed to use PAGE3 (DT2H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM2) 7 6 5 4 3 2 1 0 PWM2[9] PWM2[8] R/W-0 R/W-0 Bit 0 ~ Bit 1 (PWM2[8] ~ PWM2[9]): The Most Significant Byte of PWM1 Duty Cycle A specified value keeps the PWM1 output to stay at high until the value matches with TMR1. Bit 2 ~ Bit 7 : unused
RB (ADC input data buffer)
PAGE0 : (undefined) not allowed to use PAGE1 (ADC output data register) 7 6 5 4 3 2 1 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R R R R R R R R Bit 0 ~ Bit 7 (AD0 ~ AD7) : The last significant 8 bit of 10-bit or whole of 8 bit resolution ADC conversion output data. Combine there 8 bits and R7 PAGE1 bit4~5 as complete 10-bit ADC conversion output data in 10 bit resolution mode. PAGE2 (undefined) not allowed to use. This page is not sure to be 0 or 1 PAGE3 (PRD2: Period of PWM2) 7 6 5 4 3 2 1 0 PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 The content of this register is a period (time base) of PWM2. The frequency of PWM2 is the reverse of the period.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
16
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller RC (PORTC I/O data, Counter1 data)
PAGE0 (PORT9 I/O data register) 7 6 5 4 3 2 1 0 X X X X X PC2 PC1 X R/W R/W Bit 1 ~ Bit 2 (PC1 ~ PC2): PORTC1,PORTC2 I/O data register User can use IOC register to define input or output each bit. Bit 0; Bit 3~Bit 7: (undefined) not allowed to use. These bits are not sure to 0 or 1 PAGE1 (Counter1 data register) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CN17 CN16 CN15 CN14 CN13 CN12 CN11 CN10 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 7 (CN10 ~ CN17) : Counter1's buffer that user can read and write. Counter1 is a 8-bit up-counter with 8-bit prescaler that user can use RC PAGE1 to preset and read the counter.(write preset) After a interruption , it will reload the preset value. Example for writing : MOV 0x0C, A ; write the data at accumulator to counter1 (preset) Example for reading : MOV A, 0x0C ; read the data at counter1 to accumulator PAGE2,3 (undefined) not allowed to use. This page is not sure to 0 or 1
RD (Counter2 data)
PAGE0 (Unused) 7 6 5 4 3 2 1 0 0 0 1 0 0 0 X X R/W-0 R/W-0 R/W-0 R/W R/W R/W Bit 0 ~Bit 2 : These three bits must clear to 0 or MCU power consumption will increase. Bit 3 , Bit 7 : (undefined) not allowed to use Bit4 ~ Bit6: These 3 bits are unused, please clear bit5 and bit6 to 0 and set bit4 to 1. PAGE1 (Counter2 data register) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CN27 CN26 CN25 CN24 CN23 CN22 CN21 CN20 R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 7 (CN20 ~ CN27) : Counter2's buffer that user can read and write. Counter2 is a 8-bit up-counter with 8-bit prescaler that user can use RD PAGE1 to preset and read the counter.(write preset) After a interruption, it will reload the preset value. Example for writing : MOV 0x0D, A ; write the data at accumulator to counter2 (preset) Example for reading : MOV A, 0x0D ; read the data at counter2 to accumulator PAGE2,3 (undefined) not allowed to use. This page is not sure to 0 or 1
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
17
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller RE (Interrupt flag)
PAGE0 (Interrupt flag) 7 6 5 4 3 2 1 0 PWM2 RBF ADI PWM1 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit0 ~ Bit3 : These three bits must clear to 0 or unable to expect error will occur . Bit 4(PWM1) : PWM1 one period reach interrupt flag. Bit 5 (ADI) : ADC interrupt flag after a sampling Bit 6 (RBF) : SPI data transfer complete interrupt If SPI's RBF signal has a rising edge signal (RBF set to "1" when transfer data completely), CPU will set this bit. Bit 7(PWM2) : PWM2 one period reach interrupt flag. PAGE2,3 (undefined) not allowed to use. This page is not sure to 0 or 1
RF (Interrupt status)
(Interrupt status register) 7 6 5 4 3 2 1 0 INT3 INT0 CNT2 CNT1 TCIF R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 "1" means interrupt request, "0" means non-interrupt Bit 0(TCIF) : TCC timer overflow interrupt flag Set when TCC timer overflows. Bit 1(CNT1) : counter1 timer overflow interrupt flag Set when counter1 timer overflows. Bit 2(CNT2) : counter2 timer overflow interrupt flag Set when counter2 timer overflows. Bit 3(INT0) : external INT0 pin interrupt flag If PORT70 has a falling edge/rising edge (controlled by CONT register) trigger signal, CPU will set this bit. Bit 4~6: Unused (These bits are not sure to 0 or 1. When programmer determine what interrupt occur in subroutine, be care to note these bits) Bit 7(INT3) : external PORT73 pin interrupt flag IOCF is the interrupt mask register. User can read and clear. Trigger edge as the table Signal TCC COUNTER1 COUNTER2 INT0 INT3 Trigger Time out Time out Time out Falling Rising edge Falling edge
R10~R3F (General Purpose Register)
R10~R3F (Banks 0 ~ 3) : all are general purpose registers.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
18
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
VII.3 Special Purpose Registers
A (Accumulator)
Internal data transfer, or instruction operand holding It's not an addressable register.
CONT (Control Register)
7 6 5 4 3 2 P70EG INT TS RETBK PAB PSR2 Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1 PSR1 0 PSR0
Bit 3(PAB) : Prescaler assignment bit 0/1 TCC/WDT Bit 4(RETBK) : Return value backup control for interrupt routine 0/1 disable/enable When this bit is set to 1, the CPU will store ACC,R3 status and R5 PAGE automatically after an interrupt is triggered. And it will be restored after instruction RETI. When this bit is set to 0, the user need to store ACC, R3 and R5 PAGE in user program. Bit 5(TS) : TCC signal source 0 internal instruction cycle clock 1 16.384kHz Bit 6 (INT) : INT enable flag 0 interrupt masked by DISI or hardware interrupt 1 interrupt enabled by ENI/RETI instructions Bit 7(P70EG) : interrupt edge type of P70 0 P70 's interruption source is a rising edge signal. 1 P70 's interruption source is a falling edge signal. CONT register is readable (CONTR) and writable (CONTW). TCC and WDT : There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or WDT only at the same time. An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register. See the prescaler ratio in CONT register. Fig.8 depicts the circuit diagram of TCC/WDT.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
19
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
16.38KHz
Fig.8 Block diagram of TCC WDT IOC5 (Unused)
PAGE0 (Unused) 7 6 0 0 4 3 2 1 0 X X X X X R/W R/W R/W Bit0~4 : (undefined) not allowed to use Bit5~Bit7(Unused) : These three bits must clear to 0 or MCU power consumption will increase. The default value in these 3 bits are "1". Please clear them to "0" when init MCU. 5 0
PAGE1 (undefined) not allowed to use.(This page is not sure to 0 or 1 )
IOC6 (PORT6 I/O control, P6* pins switch control)
PAGE0 (PORT6 I/O control register) 7 6 5 4 3 2 1 0 IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 0 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit0~Bit1 (Unused) : These two bits must clear to 0 or MCU power consumption will increase. The default value in these 2 bits are "1". Please clear them to "0" when init MCU. Bit 2 ~ Bit 7 (IOC62 ~ IOC67) : PORT6(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
20
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
PAGE1 (P6* pins switch control register) 7 6 5 4 3 2 1 0 P66S P65S P64S P63S P62S 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0~Bit 1 : These 2 bits are undefined bits. Please clear them to 0. Bit 2(P62S) : Select normal I/O PORT62 pin or channel 3 input AD3 pin of ADC 0 P62 (I/O PORT62) pin is selected 1 AD3 (Channel 3 input of ADC) pin is selected Bit 3(P63S) : Select normal I/O PORT63 pin or channel 4 input AD4 pin of ADC 0 P63 (I/O PORT63) pin is selected 1 AD4 (Channel 4 input of ADC) pin is selected Bit 4(P64S) : Select normal I/O PORT64 pin or channel 5 input AD5 pin of ADC 0 P64 (I/O PORT64) pin is selected 1 AD5 (Channel 5 input of ADC) pin is selected Bit 5(P65S) : Select normal I/O PORT65 pin or channel 6 input AD6 pin of ADC 0 P65 (I/O PORT65) pin is selected 1 AD5 (Channel 6 input of ADC) pin is selected Bit 6(P66S) : Select modulation transmitting output pin of AD or I/O PORT66 pin 0 P66 (I/O PORT66) pin is selected and ADC reference voltage come from internal VDD 1 VREF (External reference voltage input of ADC) pin is selected, ADC reference voltage come from pin "ADR".
IOC7 (PORT7 I/O control, PORT7 pull high control)
PAGE0 (PORT7 I/O control register) 7 6 5 4 3 2 1 0 0 IOC76 IOC75 IOC74 IOC73 0 0 IOC70 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit1~Bit2; Bit7 (Unused) : These 3 bits must clear to 0 or MCU power consumption will increase. The default value in these 3 bits are "1". Please clear them to "0" when init MCU. Bit 0 ; Bit3~Bit6 (IOC70; IOC73~IOC76) : PORT7 I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance PAGE1 (PORT7 pull high control register) 7 6 5 4 3 2 1 0 0 PH76 PH75 PH74 PH73 0 0 PH70 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit1~Bit2; Bit7 (Unused) : These3 bits must clear to 0 or MCU power consumption will increase. Bit0 ; Bit3~Bit6 : PORT7 pull high control register 0 disable pull high function. 1 enable pull high function
IOC8 (Unused)
PAGE0 (Unused) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ** This page must clear to 0 or MCU power consumption will increase. The default value in these 8 bits are "1". Please clear them to "0" when init MCU.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
21
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
PAGE1 (Unused) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ** This page must clear to 0 or the power consumption of MCU will increase.
IOC9 (PORT9 I/O control, PORT9 switches)
PAGE0 (PORT9 I/O control register) 7 6 5 4 3 2 1 0 IOC97 IOC96 IOC95 IOC94 IOC93 IOC92 IOC91 IOC90 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 0 ~ Bit 7 (IOC90 ~ IOC97) : PORT9(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance PAGE1 (Unused) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 **These 8 bits must clear to 0 or Port9 input or output function will wronging
IOCA (Unused)
PAGE0(undefined) not allowed to use PAGE1(undefined) not allowed to use 7 6 5 4 3 2 1 0 X X X X 0 0 0 0 R/W R/W R/W-0 R/W-0 Bit0~Bit1 : Undefined registers. Please clear these two bits to 0. Bit3 , Bit6 (Unused) : These 2 bits must clear to 0 or MCU power consumption will increase. Bit2, 4,5,6 are undefined register, they are not allowed to use.
IOCB (ADC control)
PAGE0 (Unused) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ** This page must clear to 0 or MCU power consumption will increase. The default value in these 8 bits are "1". Please clear them to "0" when init MCU. PAGE1 (ADC control bits) 7 6 5 4 3 2 1 0 IN2 IN1 IN0 ADCLK1 ADCLK0 ADPWR X ADST R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0(ADST) : AD converter start to sample By setting to "1", the AD will start to sample data. This bit will be cleared by hardware automatically after a sampling. Bit 1 : (undefined) not allowed to use Bit 2(ADPWR) : AD converter power control, 1/0 enable/disable Bit 3 ~ Bit 4 (ADCLK0 ~ ADCLK1) : AD circuit `s sampling clock source.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
22
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
For PLL clock = 895.658kHz ~ 14.3MHz (CLK2~CLK0 = 001 ~ 111) ADCLK1 ADCLK0 Sampling rate Operation voltage 0 0 74.6K >=3.5V 0 1 37.4K >=3.0V 1 0 18.7K >=2.5V 1 1 9.3K >=2.5V For PLL clock = 447.829kHz (CLK2~CLK0 = 000) ADCLK1 ADCLK0 Sampling rate Operation voltage 0 0 37.4K >=3.0V 0 1 18.7K >=3.0V 1 0 9.3K >=2.5V 1 1 4.7K >=2.5V This is a CMOS multi-channel 10-bit successive approximation A/D converter. Features 74.6kHz maximum conversion speed at 5V. Adjusted full scale input External reference voltage input or internal(VDD) reference voltage 4 analog inputs multiplexed into one A/D converter Power down mode for power saving A/D conversion complete interrupt Interrupt register, A/D control and status register, and A/D data register
PLL fpll Programmable divider 1/Mx fs Divider Nx fadc 10-bit ADC ADC output
ADCLK1~ADCLK0
ENPLL
CLK2 ~ CLK0
Fig.9 ADC voltage control logic
fpll 14.331MHz 10.747MHz 7.165MHz 3.582MHz 1.791MHz 895.658kHz 447.829kHz Mx 16 12 8 4 2 1 1 fs 895.658kHz 895.658kHz 895.658kHz 895.658kHz 895.658kHz 895.658kHz 447.829kHz Nx = 1 74.638kHz 74.638kHz 74.638kHz 74.638kHz 74.638kHz 74.638kHz 37.391kHz fadcon = fadc / 12 Nx = 2 Nx = 4 37.391kHz 18.659khz 37.391kHz 18.659khz 37.391kHz 18.659khz 37.391kHz 18.659khz 37.391kHz 18.659khz 37.391kHz 18.659khz 18.659khz 9.329kHz Nx = 8 9.329kHz 9.329kHz 9.329kHz 9.329kHz 9.329kHz 9.329kHz 4.665kHz
Bit 5 ~ Bit 7(IN0~ IN2) : Input channel selection of AD converter These two bits can choose one of three AD input. IN2 IN1 IN0 Input 0 0 0 0 0 1 0 1 0 AD3 0 1 1 AD4 1 0 0 AD5 1 0 1 AD6 1 1 0 1 1 1 * This specification is subject to be changed without notice.
Pin Not select Not select P62 P63 P64 P65 Not select Not select
__________________________________________________________________________________________________________________________________________________________________
23
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller IOCC (PORTC I/O control, ADC control)
PAGE0 (Unused) 7 6 5 4 3 2 1 0 IOCC2 IOCC1 0 0 0 0 0 0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Bit 1 ~ Bit 2 (IOCC1 ~ IOCC2) : PORTC(1~2) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance ** Bit0 , Bit3 ~ Bit7 must clear to 0 or MCU power consumption will increase. The default value in these 6 un-define bits are "1". Please clear them to "0" when init MCU. PAGE1 (PORT switch) 7 6 5 4 3 2 1 0 MS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W/0 Bit 0(MS) : P6* switch mode selection 0 (default unknown) 1 ADC input mode selection (Always set this bit to "1" otherwise partial ADC function cannot be used) Bit 1 ~ Bit 7: (undefined) not allowed to use
IOCD (Clock source, Prescaler of CN1 and CN2)
PAGE0 (Reserved) PAGE1 (Clock source and prescaler for COUNTER1 and COUNTER2) 7 6 5 4 3 2 CNT2S C2_PSC2 C2_PSC1 C2_PSC0 CNT1S C1_PSC2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 2 (C1_PSC0 ~ C1_PSC2) : COUNTER1 prescaler ratio C1_PSC2 C1_PSC1 C1_PSC0 COUNTER1 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 3(CNT1S) : COUNTER1 clock source 0/1 16.384kHz/system clock Bit 4 ~ Bit 6 (C2_PSC0 ~ C2_PSC2) : COUNTER2 prescaler ratio C2_PSC2 C2_PSC1 C2_PSC0 COUNTER2 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 7(CNT2S) : COUNTER2 clock source 0/1 16.384kHz/system clock * This specification is subject to be changed without notice.
1 C1_PSC1 R/W-0
0 C1_PSC0 R/W-0
__________________________________________________________________________________________________________________________________________________________________
24
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller IOCE (Interrupt mask,)
PAGE0 (Interrupt mask) 7 6 5 4 3 2 1 0 PWM2 RBF ADI PWM1 0 0 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ Bit 3 : Undefined register. Please clear these bits to 0. Bit 4(PWM1) : PWM1 one period reach interrupt mask. Bit 5 (ADI) : ADC conversion complete interrupt mask 0/1 disable/enable interrupt There are four registers for A/D converter. Use one bit of interrupt control register (IOCE PAGE0 Bit5) for A/D conversion complete interrupt. The status and control register of A/D (IOCB PAGE1 and RE PAGE0 Bit5) responses the A/D conversion status or takes control on A/D. The A/D data register (RB PAGE1) stores A/D conversion result. ADI bit in IOCE PAGE0 register is end of A/D conversion complete interrupt enable/disable. It enables/disables ADI flag in RE register when A/D conversion is complete. ADI flag indicates the end of an A/D conversion. The A/D converter sets the interrupt flag, ADI in RE PAGE0 register when a conversion is complete. The interrupt can be disabled by setting ADI bit in IOCE PAGE0 Bit5 to `0'. The A/D converter has 4 analog input channels AD3~AD6 multiplexed into one sample and hold to A/D module. Reference voltage can be driven from VREF pin or internal power. The A/D converter itself is of an 8-bit successive approximation type and produces an 8-bit result in the RB PAGE1 data register. A conversion is initiated by setting a control bit ADST in IOCB PAGE1 Bit0. Prior to conversion, the appropriate channel must be selected by setting IN0~IN1 bits in RE register and allowed for enough time to sample data. Every conversion data of A/D need 12-clock cycle time. The minimum conversion time required is 13 us (73K sample rate). ADST Bit in IOCB PAGE1 Bit0 must be set to begin a conversion. It will be automatically reset in hardware when conversion is complete. At the end of conversion, the START bit is cleared and the A/D interrupt is activated if ADI in IOCE PAGE0 Bit5 = 1. ADI will be set when conversion is complete. It can be reset in software. If ADI = 0 in IOCE PAGE0 Bit5, when A/D start conversion by setting ADST(IOCB PAGE1 Bit0) = 1 then A/D will continue conversion without stop and hardware won't reset ADST bit. In this condition, ADI is deactived. After ADI in IOCE PAGE0 bit5 is set, ADI in RE PAGE0 bit5 will activate again. To minimum operating current , all biasing circuits in the A/D module that consume DC current are power down when ADPWR bit in IOCB PAGE1 Bit2 register is a '0'. When ADPWR bit is a `1', A/D converter module is operating. User has to set PORT62~PORT65 as AD converter input pin or bi-direction IO PORT
1 2 3 4 5 6 7 8 9 10
START SAMPLE ADI(IOCE PAGE0 bit5 ) =1 ADI(RE PAGE0 bit 5) DATA Clear by software
Fig.10 A/D converter timing
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
25
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
Bit 6 (RBF) : SPI's RBF interrupt mask 0/1 disable/enable interrupt Bit 7(PWM2) : PWM2 one period reach interrupt mask.
IOCF (Interrupt mask)
(Interrupt mask register) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INT3 INT0 CNT2 CNT1 TCIF R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 0 ~ 3 ; Bit 7 : interrupt enable bit 0 disable interrupt 1 enable interrupt Bit 4~Bit6 : (remain these values to "0"othwise it will generate unpredicted interrupts)
The status after interrupt and the interrupt sources list as the table below.
Interrupt signal GREEN mode RA(7,6)=(x,0) no SLEP Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) No function NORMAL mode RA(7,6)=(x,1) no SLEP Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0)
TCC time out IOCF bit0=1 And "ENI" COUNTER1 time out IOCF bit1=1 And "ENI" COUNTER2 time out IOCF bit2=2 And "ENI" PORT70; 3 IOCF bit3 bit7 =1 And "ENI" RBF IOCE bit6 = 1 And "ENI ADI IOCE bit5 = 1 And "ENI PWM1 IOCE bit4 = 1 And "ENI PWM2 IOCE bit7 = 1 And "ENI
Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0)
PORT70 's interrupt function is controlled by IOCF bit 3. It's falling edge or rising edge trigger (controlled by CONT register bit7). PORT73 's interrupt function is controlled by IOCF bit 7. They are falling edge trigger. ADI interrupt source function is controlled by RE PAGE0 bit 5. It is rising edge trigger after ADC sample complete. It only happens when master and 16.386kHz mode is selected.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
26
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
VII.4 I/O Port
The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers under program control. The I/O data registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig.11.
PCRD
Q
P R C L
D CLK PCWR
Q
PORT
Q
P R C L
D CLK PDWR
IOD
Q
PDRD 0 1 M U X
Fig.11_1 The circuit of I/O port and I/O control register
VDD VDD VDD
pull high
PIN
120 ohm
Fig.11_2 The input/output circuit of EM785830AA input/output ports
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
27
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
VII.5 RESET
The RESET can be caused by (1) Power on reset (2) WDT timeout. (if enabled and in GREEN or NORMAL mode) (3) /RESET pin pull low Once the RESET occurs, the following functions are performed. * The oscillator is running, or will be started. * The Program Counter (R2) is set to all "0". * When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared. * The Watchdog timer and prescaler counter are cleared. * The Watchdog timer is disabled. * The CONT register is set to all "1" * The other register (bit 7 ~ bit 0) default values are as follows. Operation registers : Address 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF R register PAGE0 00xxxxxx xxxx0000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00011xx0 xxxxxxxx xxxxxxxx xxxxx000 00000000 00000000 R register PAGE1 xxxx0000 xxxxxxxx xxxx0000 00000000 xxxxxxxx 11111111 xxxxxxxx 00000000 00000000 R register PAGE2 00000000 xxxxxxxx R register PAGE3 00000000 00000000 xxxxxx00 00000000 00000000 xxxxxx00 00000000 IOC register PAGE0 111x0000 11111111 11111111 11111111 11111111 xxxxxxxx 11111111 11111111 xxxxxxxx 0000xxxx 00000000 IOC register PAGE1
0x000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
00000000 00000000 00000000 00000000 x0xx0xx 000000x0 00000000 00000000 xxxxxxxx
VII.6 Wake-up
The controller provided sleep mode for power saving : SLEEP mode, RA(7) = 0 + "SLEP" instruction The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or PLL control (which has enable register), user has to turn it off by software. Wake-up from SLEEP mode (1) WDT time out (2) External interrupt (3) /RESET pull low All these cases will reset controller , and run the program at address zero. The status just like the power on reset.
VII.7 Interrupt
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
28
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
VII.8 Instruction Set
Instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register. The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. INSTRUCTION BINARY 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0000 0001 0010 0011 0100 rrrr 0000 0001 0010 0011 HEX 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr MNEMONIC NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R OPERATION No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC Enable Interrupt CONT A IOCR A R2+A R2 bits 9,10 do not clear AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A&RA A&RR ARA ARR A+RA A+RR RA RR /R A STATUS AFFECTED None C None T,P T,P None None None None None None None Z,C,DC None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Instruction cycle 1 1 1 1 1 1 1 1 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 01rr rrrr 1000 0000 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
29
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
0 0 0 0 0 0 0100 0101 0101 0101 0101 0110 11rr 00rr 01rr 10rr 11rr 00rr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1E8k 1Fkk COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT PAGE k ADD A,k /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1) R(0) C, C A(7) R(n) R(n-1) R(0) C, C R(7) R(n) A(n+1) R(7) C, C A(0) R(n) R(n+1) R(7) C, C R(0) R(0-3) A(4-7) R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP] (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP] 001H PC K->R5(4:0) k+A A Z Z Z None None C C C C None None None None None None None None None None None Z Z Z None Z,C,DC None None Z,C,DC 1 1 1 2 if skip 2 if skip 1 1 1 1 1 1 2 if skip 2 if skip 1 1 2 if skip 2 if skip 2 2 1 1 1 1 2 1 1 1 1
0 0110 01rr 0 0110 10rr 0 0110 11rr 0 0111 00rr 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0111 0111 0111 100b 101b 110b 111b 00kk 01kk 1000 1001 1010 1011 1100 1101 1110
01rr rrrr 10rr rrrr 11rr rrrr bbrr rrrr bbrr rrrr bbrr rrrr bbrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0001
1 1110 100k kkkk 1 1111 kkkk kkkk
** 1 Instruction cycle = 2 main CLK
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
30
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
VII.9 Code Option
CODE Option Register
13 12 11 0 10 0 9 1 8 7 6 5 4 3 MER 2 1 0
Bit 3(MER) : Memory error recover function 0 disable memory error recover function 1 enable memory error recovery function If user enable memory error recovery function, MCU will improve effect from environment noise. Bit 9: This bit must set to 1. Bit10 ~ Bit11 : These 2 bits must clear to 0.
VII.10 Dual sets of PWM (Pulse Width Modulation)
(1) Overview In PWM mode, both PWM1 and PWM2 pins produce up to a 10-bit resolution PWM output (see. Fig.12 for the functional block diagram). A PWM output has a period and a duty cycle, and it keeps the output in high. The baud rate of the PWM is the inverse of the period. Fig.13 depicts the relationships between a period and a duty cycle.
DL2H + DL2L
latch
To PWM1IF
Fosc 1:2 1:8 1:32 1:64
DT2H + DT2L Comparator MUX
TMR1H + TMR1L
reset
Duty Cycle Match
PWM1 R S
IOC6
Q
Comparator
T1P0 T1P1 T1EN
Period Match
PRD1 Data Bus
DL2H + DL2L
latch
Data Bus
To PWM2IF
T2P0 T2P1 T2EN
DT2H + DT2L
Comparator
Duty Cycle Match
PWM2 Fosc 1:2 1:8 1:32 1:64
TMR2H + TMR2L
reset
R S
Q
MUX Comparator
IOC6 Period Match
PRD2
Fig.12 The Functional Block Diagram of the Dual PWMs
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
31
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
Period
Duty Cycle DT1 = TMR1
PRD1 = TMR1
Fig.13 The Output Timing of the PWM
(2) Increment Timer Counter ( TMRX: TMR1H/TWR1L or TMR2H/TWR2L ) TMRX are ten-bit clock counters with programmable prescalers. They are designed for the PWM module as baud rate clock generators. TMRX can be read, written, and cleared at any reset conditions. If employed, they can be turned down for power saving by setting T1EN bit [PWMCON<4>] or T2EN bit [PWMCON<5>] to 0. (3) PWM Period ( PRDX : PRD1 or PRD2 ) The PWM period is defined by writing to the PRDX register. When TMRX is equal to PRDX, the following events occur on the next increment cycle: * TMRX is cleared. * The PWMX pin is set to 1. * The PWM duty cycle is latched from DT1/DT2 to DTL1/DTL2. < Note > The PWM output will not be set, if the duty cycle is 0; * The PWMXIF pin is set to 1. The following formula describes how to calculate the PWM period: PERIOD = (PRDX + 1) * 4 * (1/Fosc) * (TMRX prescale value ) Where Fosc is system clock (4) PWM Duty Cycle ( DTX: DT1H/ DT1L and DT2H/ DT2L; DTL: DL1H/DL1L and DL2H/DL2L ) The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded at any time. However, it cannot be latched into DTL until the current value of DLX is equal to TMRX. The following formula describes how to calculate the PWM duty cycle: Duty Cycle = (DTX) * (1/Fosc) * (TMRX prescale value ) (5) PWM Programming Procedures/Steps Load PRDX with the PWM period. (1) Load DTX with the PWM Duty Cycle. (2) Enable interrupt function by writing IOCF PAFE0, if required. (3) Set PWMX pin to be output by writing a desired value to IOCC PAGE0. (4) Load a desired value to R5 PAGE3 with TMRX prescaler value and enable both PWMX and TMRX. (6) Timer Timer1 (TMR1) and Timer2 (TMR2) (TMRX) are 10-bit clock counters with programmable prescalers, respectively. They are designed for the PWM module as baud rate clock generators. TMRX can be read, written, and cleared at any reset conditions. The figure in the next page shows TMRX block diagram. Each signal and block are described as follows:
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
32
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
Fosc 1:2 1:8 1:32 1:64
To PWM1IF
MUX TMR1X
reset Period Match
Comparator
T1P0 T1P1 T1EN
PRD1 Data Bus Data Bus
PRD2
T2P0 T2P1 T2EN
Comparator
Period Match
Fosc 1:2 1:8 1:32 1:64
TMR2X MUX
reset
To PWM2IF
*TMR1X = TMR1H + TMR1L; *TMR2X = TMR2H +TMR2L
Fig.14 TMRX Block Diagram
* Fosc: Input clock. * Prescaler ( T1P0 and T1P1/T2P1 and T2P0 ): Options of 1:2, 1:8, 1:32, and 1:64 are defined by TMRX. It is cleared when any type of reset occurs. * TMR1X and TMR2X (TMR1H/TWR1L and TMR2H/TMR2L ):Timer X register; TMRX is increased until it matches with PRDX, and then is reset to 0. TMRX cannot be read. * PRDX ( PRD1 and PRD2 ): PWM period register. When defining TMRX, refer to the related registers of its operation as shown in prescale register. It must be noted that the PWMX bits must be disabled if their related TMRXs are employed. That is, bit 7 and bit 6 of the PWMCON register must be set to `0'. Related Control Registers(R5 PAGE3) of TMR1 and TMR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 PWM2E PWM1E T2EN T1EN T2P1 T2P0 T1P1 Bit 0 T1P0
Timer programming procedures/steps (1) Load PRDX with the TIMER period. (2) Enable interrupt function by writing IOCF PAGE0, if required (3) Load a desired value to PWMCON with the TMRX prescaler value and enable both TMRX and disable PWMX.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
33
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
VIII. Absolute Operation Maximum Ratings
RATING DC SUPPLY VOLTAGE INPUT VOLTAGE OPERATING TEMPERATURE RANGE SYMBOL VDD Vin Ta VALUE -0.3 To 6 -0.5 to VDD +0.5 0 to 70 UNIT V V J
IX. DC Electrical Characteristic
(Ta = 25C, AVDD=VDD=5V5%, VSS=0V) Parameter Symbol Condition Min Input leakage current for IIL1 VIN = VDD, VSS input pins Input leakage current for biIIL2 VIN = VDD, VSS directional pins Input high voltage VIH 2.5 Input low voltage VIL Input high threshold voltage VIHT /RESET, TCC 2.0 Input low threshold voltage VILT /RESET, TCC Clock input high voltage VIHX OSCI 3.5 Clock input low voltage VILX OSCI Output high voltage for VOH1 IOH = -6mA 2.4 PORTC1~PORTC2 Output high voltage for VOH2 IOH = -10mA 2.4 PORT62~PORT67; PORT7 Output high voltage for VOH3 IOH = -20mA 2.4 PORT9 Output low voltage for VOL1 IOH = 6mA PORTC1~PORTC2 Output low voltage for VOL2 IOH = 10mA PORT62~PORT67; PORT7 Output low voltage for VOL3 IOH = 20mA PORT9 Pull-high current IPH Pull-high active input pin at VSS Power down current ISB1 All input and I/O pin at VDD, (SLEEP mode) output pin floating, WDT disabled Low clock current ISB2 CLK=32.768KHz, All analog (GREEN mode) circuits disabled, All input and I/O pin at VDD, output pin floating, WDT disabled pin floating, WDT disabled Operating supply current ICC1 /RESET=High, (Normal mode) CLK=3.582MHz, All analog circuits disabled, output pin floating Typ Max 1 1 Unit A A V V V V V V V V V 0.4 0.4 0.4 -10 4 -15 8 V V V A A A
0.8 0.8 1.5
35
50
1
2
mA
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
34
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
XI. AC Electrical Characteristic
CPU instruction timing (Ta = 25C, AVDD=VDD=5V, VSS=0V) Parameter Input CLK duty cycle Instruction cycle time Device delay hold time TCC input period Watchdog timer period Symbol Dclk Tins Tdrh Ttcc Twdt Condition 32.768kHz 3.582MHz Note 1 Ta = 25C (Tins+20)/N 16 Min 45 Typ 50 60 550 16 Max 55 Unit % us ns ms ns ms
Note 1: N= selected prescaler ratio. ADC characteristic (VDD = 5V, Ta = +25C, for internal reference voltage) Parameter Symbol Condition Upper bound offset voltage Vofh Lower bound offset voltage Vofl *These parameters are characterized but not tested. * About ADC characteristic, please refer to next page. Timing characteristic (AVDD=VDD=5V,Ta=+25C) Description Oscillator timing characteristic OSC start up Min Typ 44 32 Max 52.8 38.4 Unit mV mV
Symbol Min Typ Max Unit
1500 10 ms us ns ns ns ns ns ns ns ns uS mS
32.768kHz Toscs 400 3.579MHz PLL 5 SPI timing characteristic (CPU clock 3.58MHz and Fsco = 3.58Mhz /2) /SS set-up time Tcss 560 /SS hold time Tcsh 250 SCLK high time Thi 250 SCLK low time Tlo 250 SCLK rising time Tr 15 SCLK falling time Tf 15 SDI set-up time to the reading edge of SCLK Tisu 25 SDI hold time to the reading edge of SCLK Tihd 25 SDO disable time Tdis Timing characteristic of reset The minimum width of reset low pulse Trst 3 The delay between reset and program start Tdrs 18
30 30
560
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
35
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
VDD
OSC
Toscs
Power on reset
Trst
/RESET
Tdrs Tdrs
Program Active
The relative between OSC stable time and power on reset
EM78P5830A operation voltage(X axis
MHz
min VDD ; Y axis
main CLK):
14.33 10.74 7.16 3.58 1.79
V 2.2 2.5 3.0 3.6 4 5.5
Fig.15 The relative between operating voltage and main CLK
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
36
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller EM785830AA's 10 bit ADC characteristic
EM785830AA build in 10 bit resolution, multi channel ADC function. In ideal, if ADC's reference voltage is 5V, the ADC's LSB will be 5V/1024. But in practical, for some physics or circuit's character, some un-ideal will effect the converter result. As the next figure, offset voltage will reduce AD's converter range. If AD's input voltage less than VOFL, ADC will output 0; in opposition, if input voltage is larger than (VDD-VOFH), ADC will output 1023. That is to say the physics AD converter range will replace by (VDD-VOFH+LSB-VOFL+LSB). If we defined that VRB = VOFL - LSB and VRT = VDD-VOFH+LSB, the physics LSB is: LSB = (VRT - VRB) / 1024 = (VDD - (VOFH+VOFL) ) / 1022 For real operating, please think about the effect of AD's offset voltage. If converter the range of (VRT - VRB), the AD converter's opposite result will be precised.
10-bit ADC
VDD VRT Min. input for ADC output = 1023 VOFH
(For 10-bit ADC, internally it takes this range to average 1024 steps)
Min. input for ADC output = 1 VOFL VRB 0V
Fig.16 The relative between ADC and offset voltage
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
37
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
XII. Timing Diagrams
ins
Fig.17 AC timing
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
38
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
Appendix I: Describe of EM78P5830A/AA (only list the difference between mask and OTP)
The EM78P5830A is an 8-bit RISC type microprocessor with low power, high speed CMOS technology. There are 16Kx13 bits Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides security bits and some One time programmable Option bits to protect the OTP memory code from any external access as well as to meet user's options. This integrated single chip has an on_chip watchdog timer (WDT), program OTP-ROM, data RAM, programmable real time clock/counter, internal interrupt, power down mode, built-in three-wire SPI, dual PWM(Pulse Width Modulation), 4-channel 10-bit A/D converter and tri-state I/O.
Feature
CPU
E Operating voltage : 2.2V~5.5V at main CLK less then 3.58MHz. Main CLK(Hz) Under 3.58M 7.16M 10.74M 14.3M Operating Voltage(min) 2.2 2.5 3 3.6 E 16k x 13 on chip Electrical One Time Programmable Read Only Memory (OTP-ROM) E 0.5k x 8 on chip data RAM E Up to 21 bi-directional tri-state I/O ports(4 shared with AD input; 1 shared with external interrupt input ) E 16 level stack for subroutine nesting E 8-bit real time clock/counter (TCC) E two 8-bit counters : COUNTER1 and COUNTER2 E On-chip watchdog timer (WDT) E 99.9H single instruction cycle commands E Three modes (Main clock can be programmed from 447.829k to 14.3MHz generated by internal PLL) Mode CPU status Main clock 32.768kHz clock status Sleep mode Turn off Turn off Turn off Green mode Turn on Turn off Turn on Normal mode Turn on Turn on Turn on E 7 level Normal mode frequency : 447.8K , 895.7K , 1.79M , 3.58M , 7.16M , 10.75M and 14.3MHz. E Input port interrupt function E Dual clocks operation (Internal PLL main clock , External 32.768KHz)
SPI
E E E E Serial Peripheral Interface (SPI) : a kind of serial I/O interface Interrupt flag available for the read buffer full, Programmable baud rates of communication Three-wire synchronous communication. (shared with IO)
PWM
E Dual PWM (Pulse Width Modulation) with 10-bit resolution E Programmable period (or baud rate) E Programmable duty cycle
ADC
E Operating : 2.5Va 5.5V E 4 channel 10-bit successive approximation A/D converter E Internal (VDD) or external reference
POR
E 2.0V Power-on voltage detector reset
PACKAGE
28 pin PDIP and SOP package(300 mil)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
39
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
One time programmable ROM burner pin OTP PIN NAME MASK ROM PIN NAME VDD AVDD VPP /RESET DINCK P65 ACLK P64 PGMB P63 OEB P62 DATA P73 GND AVSS P.S.
EM78P5830A CODE Option Register
13 12 11 0 10 0 9 1 8 7 6 5 4 3 MER 2 1 0 /POT0
Bit 0 (/POT0): program ROM protect option. If set 1 to the bit, program memory can be access; else if clear this bit , program memory can not be access. Bit 3(MER) : Memory error recover function 0 disable memory error recover function 1 enable memory error recovery function If user enable memory error recovery function, MCU will improve effect from environment noise. Bit 9: Please set this bit to 1. Bit 10: Please clear this bit to 0. Bit 11: Please clear this bit to 0.
DC Electrical Characteristic
(Ta = 25C, AVDD=VDD=5V5%, VSS=0V) Parameter Symbol Condition Output high voltage for VOH2 IOH = -10mA PORT62~PORT67 Output high voltage for VOH3 IOH = -20mA PORT7 ; PORT9 Output low voltage for VOL2 IOH = 10mA PORT62~PORT67 Output low voltage for VOL3 IOH = 20mA PORT7 ; PORT9 Min 2.4 2.4 0.4 0.4 Typ Max Unit V V V V
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
40
12/1/2004 V1.6
EM785830AA 8-bit Micro-controller
Appendix II: Package spec of EM785830AA, EM78P5830A/AA
EM785830AAP, EM78P5830AP, EM78P5830AAP
EM785830AAM, EM78P5830AM, EM78P5830AAM
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
41
12/1/2004 V1.6

▲Up To Search▲

Price & Availability of EM78P5830AA

	To Download EM78P5830AA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .